[clang][ARM] relax -mtp=cp15 for non-thumb cases
authorNick Desaulniers <ndesaulniers@google.com>
Fri, 3 Dec 2021 21:59:46 +0000 (13:59 -0800)
committerNick Desaulniers <ndesaulniers@google.com>
Fri, 3 Dec 2021 22:00:00 +0000 (14:00 -0800)
commit9f95bc7dc18390199553cf2ea3bfcdc6a95717ef
tree1398c45b4e7c8427d952d3181ca1f8432db921d2
parent728b982bb2aec5a5e9c887a7b0181ee360b27b54
[clang][ARM] relax -mtp=cp15 for non-thumb cases

Building -march=armv6k Linux kernels with -mtp=cp15 fails to
compile:

error: hardware TLS register is not supported for the arm
sub-architecture

@ardb found docs for ARM1176JZF-S (ARMv6K) that reference hard thread
pointer.

Relax our ARMv6 check for cases where we're targeting ARM via -marm (vs
Thumb1 via -mthumb).  This more closely matches the KConfig requirements
for where we plan to use these (ie. ARMv6K, ARMv7 (arm or thumb2)).

As @peter.smith mentions:
  on armv5 we can write the instruction to read/write to CP15 C13 with
  the ThreadID opcode. However on no armv5 implementation will the CP15
  C13 have a Thread ID register. The GCC intent seems to be whether the
  instruction is encodable rather than check what the CPU supports.

Link: https://github.com/ClangBuiltLinux/linux/issues/1502
Link: https://developer.arm.com/documentation/ddi0301/h/system-control-coprocessor/system-control-processor-registers/c13--thread-and-process-id-registers
Reviewed By: ardb, peter.smith

Differential Revision: https://reviews.llvm.org/D114116
clang/lib/Driver/ToolChains/Arch/ARM.cpp
clang/lib/Driver/ToolChains/Arch/ARM.h
clang/test/Driver/clang-translation.c