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[RISCV] Add patterns for vector narrowing integer right shift instructions
authoreopXD <eop.chen@sifive.com>
Mon, 17 Jan 2022 07:40:00 +0000 (23:40 -0800)
committereopXD <eop.chen@sifive.com>
Wed, 19 Jan 2022 06:30:13 +0000 (22:30 -0800)
commit9f27941c2fbb9ab032dde554b323e91793452625
treebc6ce19e03d9d9f4a78016ad7709998ebcce6b86tree | snapshot
parentd7c8d51f94139b31f6dc2dbcb1a52958ffaa5da3commit | diff
[RISCV] Add patterns for vector narrowing integer right shift instructions

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117454
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll [new file with mode: 0644] blob
Domain: System / Toolchain;