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author	eopXD <yueh.ting.chen@gmail.com>
	Wed, 14 Jun 2023 01:35:14 +0000 (18:35 -0700)
committer	eopXD <yueh.ting.chen@gmail.com>
	Tue, 20 Jun 2023 18:09:24 +0000 (11:09 -0700)
commit	9ed668ad93218ab2fe062c977d89f486056b4e56
tree	56eaa8ea0ac86605db463328205af790a72c2245	tree \| snapshot
parent	5510f0b8f4b1400905194f0c75acb41c6b1c21ce	commit \| diff

[RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu

Depends on D151397.

This patch follows the patch-set of D151395. This patch seeks to
update all the remaining fixed-point intrinsics to model vxrm
control, adding rounding mode control for `vsmul`, `vssra`,
`vssrl`, `vnclip`, and `vnclipu`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152879

45 files changed:

clang/include/clang/Basic/riscv_vector.td		diff \| blob \| history
clang/lib/Sema/SemaChecking.cpp		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vnclip-out-of-range.c	[new file with mode: 0644]	blob
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vnclipu-out-of-range.c	[new file with mode: 0644]	blob
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-out-of-range.c	[new file with mode: 0644]	blob
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vssra-out-of-range.c	[new file with mode: 0644]	blob
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vssrl-out-of-range.c	[new file with mode: 0644]	blob
llvm/include/llvm/IR/IntrinsicsRISCV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/masked-tama.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vnclip.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vnclipu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll		diff \| blob \| history

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