Merge branch 'CR_930_V4L2_changhuang.liang' into 'jh7110_fpga_dev_5.15'
authorandy.hu <andy.hu@starfivetech.com>
Fri, 6 May 2022 11:57:40 +0000 (11:57 +0000)
committerandy.hu <andy.hu@starfivetech.com>
Fri, 6 May 2022 11:57:40 +0000 (11:57 +0000)
commit9e9c190ace17feb7d386bf952bf64ace517fcd36
tree525fab90f995b98cdb599a3fcac2f4be6dfd50b1
parentaa576c7bc573d90bfd646af95bee72685ad39e42
parenta892d9a49a35cbb5884b9fb80eb61fe2ea1866f8
Merge branch 'CR_930_V4L2_changhuang.liang' into 'jh7110_fpga_dev_5.15'

V4L2: fixed code warning!

See merge request sdk/sft-riscvpi-linux-5.10!52
arch/riscv/boot/dts/starfive/jh7110.dtsi