[PowerPC] Add new DMR register classes to Future CPU.
authorStefan Pintilie <stefanp@ca.ibm.com>
Wed, 2 Nov 2022 14:55:54 +0000 (09:55 -0500)
committerStefan Pintilie <stefanp@ca.ibm.com>
Thu, 3 Nov 2022 13:29:55 +0000 (08:29 -0500)
commit9df924a634ac5ea702b0d8d0d8b737c819a98095
treede4da83c2899eefe8d671774b72d8f16172ef803
parent592a96c03b0c587404e78d69bbf072609b1e6417
[PowerPC] Add new DMR register classes to Future CPU.

A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.

This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.

Reviewed By: amyk, saghir

Differential Revision: https://reviews.llvm.org/D136366
19 files changed:
llvm/include/llvm/CodeGen/ValueTypes.td
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Support/MachineValueType.h
llvm/lib/CodeGen/ValueTypes.cpp
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
llvm/lib/Target/PowerPC/PPCInstrFuture.td [new file with mode: 0644]
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td [new file with mode: 0644]
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td [new file with mode: 0644]
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/test/CodeGen/PowerPC/future-check-features.ll
llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt [new file with mode: 0644]
llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt [new file with mode: 0644]
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s [new file with mode: 0644]
llvm/utils/TableGen/CodeGenTarget.cpp