arm64: Refactor sysinstr exception handling
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Fri, 9 Sep 2016 13:07:15 +0000 (14:07 +0100)
committerWill Deacon <will.deacon@arm.com>
Fri, 9 Sep 2016 14:03:29 +0000 (15:03 +0100)
commit9dbd5bb25c56e35e6b4c34d968689a1ded850924
treef81f727180de3d8eef52c1d69d72a46cc196eea5
parent072f0a633838aca13b5a8b211eb64f5c445cfd7c
arm64: Refactor sysinstr exception handling

Right now we trap some of the user space data cache operations
based on a few Errata (ARM 819472, 826319, 827319 and 824069).
We need to trap userspace access to CTR_EL0, if we detect mismatched
cache line size. Since both these traps share the EC, refactor
the handler a little bit to make it a bit more reader friendly.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm64/include/asm/esr.h
arch/arm64/kernel/traps.c