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(parent: a711f38) | patch
[VTA][TSIM] add virtual memory support to tsim example (#3868)
authorLuis Vega <vegaluisjose@users.noreply.github.com>
Sun, 1 Sep 2019 00:49:17 +0000 (17:49 -0700)
committerThierry Moreau <moreau@uw.edu>
Sun, 1 Sep 2019 00:49:17 +0000 (17:49 -0700)
commit9d880bd3d12f08edd265314fe51dc5810d541328
tree2e61e0f06bf495d57b89ab72bf457dad775d90c2tree | snapshot
parenta711f38ebe5fd27033bdad1e49fcd3b929c92ea4commit | diff
[VTA][TSIM] add virtual memory support to tsim example (#3868)

* [VTA][TSIM] add virtual memory support to tsim example

* fix identation

* remove USE_TSIM macro and use 32-bit addr instead
vta/apps/tsim_example/CMakeLists.txt diff | blob | history
vta/apps/tsim_example/README.md diff | blob | history
vta/apps/tsim_example/python/tsim.py diff | blob | history
vta/apps/tsim_example/src/driver.cc diff | blob | history
vta/apps/tsim_example/tests/python/chisel_accel.py diff | blob | history
vta/apps/tsim_example/tests/python/verilog_accel.py diff | blob | history
Domain: Machine Learning / ML Framework;