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soc: mediatek: mmsys: Add sw0_rst_offset for MT8192
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Wed, 23 Mar 2022 09:19:32 +0000 (10:19 +0100)
committerMatthias Brugger <matthias.bgg@gmail.com>
Mon, 4 Apr 2022 12:10:02 +0000 (14:10 +0200)
commit9d7370a56d1871e924377872985a13f6cd104e82
tree8aa645b6a68b7a9005855ce372ce954e5783ae2dtree | snapshot
parent3123109284176b1532874591f7c81f3837bbdc17commit | diff
soc: mediatek: mmsys: Add sw0_rst_offset for MT8192

MT8192 has the same sw0 reset offset as MT8186: add the parameter
to be able to use mmsys as a reset controller for managing at
least the DSI reset line.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220323091932.10648-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
drivers/soc/mediatek/mtk-mmsys.c diff | blob | history
Domain: System / Kernel;