powerpc/perf: Update Power PMU cache_events to u64 type
authorAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Fri, 17 Jul 2020 14:38:15 +0000 (10:38 -0400)
committerMichael Ellerman <mpe@ellerman.id.au>
Wed, 22 Jul 2020 11:56:40 +0000 (21:56 +1000)
commit9d4fc86dcd510dab5521a6c891f9bf379b85a7e0
tree7f885b485a5a633a65f94b79469afeb7619beec8
parent7e4a145e5b675d5a9182f756950f001eaa256795
powerpc/perf: Update Power PMU cache_events to u64 type

Events of type PERF_TYPE_HW_CACHE was described for Power PMU
as: int (*cache_events)[type][op][result];

where type, op, result values unpacked from the event attribute config
value is used to generate the raw event code at runtime.

So far the event code values which used to create these cache-related
events were within 32 bit and `int` type worked. In power10,
some of the event codes are of 64-bit value and hence update the
Power PMU cache_events to `u64` type in `power_pmu` struct.
Also propagate this change to existing all PMU driver code paths
which are using ppmu->cache_events.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-4-git-send-email-atrajeev@linux.vnet.ibm.com
arch/powerpc/include/asm/perf_event_server.h
arch/powerpc/perf/core-book3s.c
arch/powerpc/perf/generic-compat-pmu.c
arch/powerpc/perf/mpc7450-pmu.c
arch/powerpc/perf/power5+-pmu.c
arch/powerpc/perf/power5-pmu.c
arch/powerpc/perf/power6-pmu.c
arch/powerpc/perf/power7-pmu.c
arch/powerpc/perf/power8-pmu.c
arch/powerpc/perf/power9-pmu.c
arch/powerpc/perf/ppc970-pmu.c