[RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmani...

[RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

The 0.93 spec has this implementation for add.uw

uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {
  uint_xlen_t rs1u = (uint32_t)rs1;
  return rs1u + rs2;
}

The 0.92 spec had the usages of rs1 and rs2 swapped.

Reviewed By: frasercrmck, asb

Differential Revision: https://reviews.llvm.org/D95090