[CodeGen] Rename functions PrintReg* to printReg*
authorFrancis Visoiu Mistrih <francisvm@yahoo.com>
Tue, 28 Nov 2017 12:42:37 +0000 (12:42 +0000)
committerFrancis Visoiu Mistrih <francisvm@yahoo.com>
Tue, 28 Nov 2017 12:42:37 +0000 (12:42 +0000)
commit9d419d3b0cfda0f85d88633bd8620cd65ccb0498
treee1fa028a9c3a8d514e67b9bac321519331979dea
parent8dc603b03147c91ff4e66b8bfc934aad6c4cb4b3
[CodeGen] Rename functions PrintReg* to printReg*

LLVM Coding Standards:
  Function names should be verb phrases (as they represent actions), and
  command-like function should be imperative. The name should be camel
  case, and start with a lower case letter (e.g. openFile() or isFoo()).

Differential Revision: https://reviews.llvm.org/D40416

llvm-svn: 319168
67 files changed:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/AllocationOrder.cpp
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/DetectDeadLanes.cpp
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/GlobalISel/Localizer.cpp
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/LiveInterval.cpp
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/lib/CodeGen/LiveIntervalUnion.cpp
llvm/lib/CodeGen/LivePhysRegs.cpp
llvm/lib/CodeGen/LiveRangeCalc.cpp
llvm/lib/CodeGen/LiveRangeEdit.cpp
llvm/lib/CodeGen/LiveRegMatrix.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/MachineTraceMetrics.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/PHIElimination.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/RegisterClassInfo.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/CodeGen/RegisterPressure.cpp
llvm/lib/CodeGen/RegisterScavenging.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/ScheduleDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/CodeGen/SplitKit.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/CodeGen/VirtRegMap.cpp
llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
llvm/lib/Target/ARC/ARCInstrInfo.cpp
llvm/lib/Target/ARC/ARCRegisterInfo.cpp
llvm/lib/Target/ARM/A15SDOptimizer.cpp
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/Hexagon/BitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/RDFLiveness.cpp
llvm/lib/Target/Hexagon/RDFRegisters.cpp