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(parent: 9877a34) | patch
spi: tegra114: add 3 wire transfer mode support
authorSowjanya Komatineni <skomatineni@nvidia.com>
Fri, 5 Apr 2019 00:14:08 +0000 (17:14 -0700)
committerMark Brown <broonie@kernel.org>
Mon, 8 Apr 2019 07:12:26 +0000 (14:12 +0700)
commit9d199231b000414e420a35912760f2d67e9c56d7
tree8cba37fd6bfb4e6f5e5bdf152647282c085753c4tree | snapshot
parent9877a347f2056f7aa4e770de9a20048ad288f545commit | diff
spi: tegra114: add 3 wire transfer mode support

This patch adds 3 wire transfer support to SPI mode list along with
its implementation.

3 wire or Bi-directional mode uses only one serial data pin for the
transfer. SPI in master mode uses MOSI data line only and MISO data
line is not used.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-tegra114.c diff | blob | history
Domain: System / Kernel;