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(parent: 0bc8875) | patch
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:12 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 28 Mar 2023 03:23:09 +0000 (12:23 +0900)
commit9cfecb805dadda4d8c0801fe1b52aa377707fe1b
treec9ad40256242c14d5162b8738e78c8fb97a4674etree | snapshot
parent0bc887536b04b9f5e97a0038798538f2147031e5commit | diff
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

Add PLL clock inputs from PLL clock generator.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml diff | blob | history
Domain: System / Kernel;