[RISCV] Add intrinsics for vector AMO operations
authorShihPo Hung <shihpo.hung@sifive.com>
Fri, 8 Jan 2021 06:51:37 +0000 (22:51 -0800)
committerShihPo Hung <shihpo.hung@sifive.com>
Tue, 19 Jan 2021 07:11:10 +0000 (23:11 -0800)
commit9cf511aa08ae2a5b94e9cefe3fc60cc33358519b
tree21b0500c69e36651908382d5ca824dba5c6b49b3
parent9a0900dc4c6b3390fc886b7b556196da82ba1204
[RISCV] Add intrinsics for vector AMO operations

Add vamoswap, vamoadd, vamoxor, vamoand, vamoor,
    vamomin, vamomax, vamominu, vamomaxu intrinsics.

Reviewed By: craig.topper, khchen

Differential Revision: https://reviews.llvm.org/D94589
20 files changed:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll [new file with mode: 0644]