drm/amd/display: Fix updating infoframe for DCN3.1 eDP
authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Wed, 16 Jun 2021 21:11:12 +0000 (17:11 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 8 Jul 2021 19:15:03 +0000 (15:15 -0400)
commit9cb2f2df669ec7abd9c4421fe8af6e50e920d5bf
tree9ff10dd1729234b8f9607ff0c4bfd2455ad788bf
parent46db138dc83ae16e188038358c925c560110f804
drm/amd/display: Fix updating infoframe for DCN3.1 eDP

[Why]
We're only treating TMDS as a valid target for infoframe updates which
results in PSR being unable to transition from state 4 to state 5.

[How]
Also allow infoframe updates for DCN3.1 - following how we handle
this path for earlier ASIC as well.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c