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[X86][AVX] Combine 128/256-bit lane shuffles with zeroable upper subvectors to EXTRAC...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 29 Mar 2020 18:44:39 +0000 (19:44 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 29 Mar 2020 18:51:38 +0000 (19:51 +0100)
commit9c8ec99c80a5ad9b21d424d77fb19f825319b284
tree952eb46e28e2ef33924cc6c34b0ba4fa4c38ca75tree | snapshot
parentfe0723dc9d45acfa4511961b208b7817b09297eccommit | diff
[X86][AVX] Combine 128/256-bit lane shuffles with zeroable upper subvectors to EXTRACT_SUBVECTOR (PR40720)

As explained on PR40720, EXTRACTF128 is always as good/better than VPERM2F128/SHUF128, and we can use the implicit zeroing of the uppers.
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/vector-reduce-mul.ll diff | blob | history
llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll diff | blob | history
Domain: System / Toolchain;