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author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Thu, 11 Feb 2016 06:02:01 +0000 (06:02 +0000)
committer	Matt Arsenault <Matthew.Arsenault@amd.com>
	Thu, 11 Feb 2016 06:02:01 +0000 (06:02 +0000)
commit	9c47dd583a94f457411df5403eff4228cc3690cd
tree	bf0d49daf75b9ec932dc33135e9c6c8c193d9f3c	tree \| snapshot
parent	4244be25bd7c438ac755813ff33e6e80ca6b6f34	commit \| diff

AMDGPU: Remove some old intrinsic uses from tests

llvm-svn: 260493

66 files changed:

llvm/test/CodeGen/AMDGPU/add_i64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/addrspacecast.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/commute-compares.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/commute_modifiers.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds_read2.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds_read2st64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds_write2.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds_write2st64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fabs.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/flat-address-space.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fma-combine.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fmuladd.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fp-classify.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/indirect-private-64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mad-combine.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mad-sub.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/madak.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/madmk.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/max.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/max3.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-stores.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/min.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/min3.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/mubuf.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/operand-folding.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/rsq.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/salu-to-valu.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/shl_add_constant.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/store-barrier.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/v_cndmask.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/valu-i1.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/vop-shrink.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/wait.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll		diff \| blob \| history
llvm/test/Transforms/CodeGenPrepare/AMDGPU/no-sink-addrspacecast.ll		diff \| blob \| history
llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-barrier.ll		diff \| blob \| history
llvm/test/Transforms/StructurizeCFG/nested-loop-order.ll		diff \| blob \| history

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