platform/x86: intel_pmc_core: Add LTR IGNORE debug feature

platform/x86: intel_pmc_core: Add LTR IGNORE debug feature

SPT LTR_IGN register provides a means to make the PMC ignore the LTR values
reported by the individual PCH devices.

echo <IP Offset> > /sys/kernel/debug/pmc_core/ltr_ignore.

When a particular IP Offset bit is set the PMC will ignore the LTR value
reported by the corresponding IP when the PMC performs the latency
coalescing.

IP Offset	IP Name
0		SPA
1		SPB
2		SATA
3		GBE
4		XHCI
5		RSVD
6		ME
7		EVA
8		SPC
9		Azalia/ADSP
10		RSVD
11		LPSS
12		SPD
13		SPE
14		Camera
15		ESPI
16		SCC
17		ISH

Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
[dvhart: pmc_core_ltr_ignore_write local declaration order cleanup]
Signed-off-by: Darren Hart <dvhart@linux.intel.com>