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(parent: 63a92fe) | patch
cxgb4: Fix T5 adapter accessing T4 adapter registers
authorHariprasad Shenai <hariprasad@chelsio.com>
Mon, 1 Sep 2014 14:24:57 +0000 (19:54 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 2 Sep 2014 06:00:41 +0000 (23:00 -0700)
commit9bb59b96ae88ee9dc035d5cc9818b02b12208904
tree4e6795065995b7e9e126c0133c8e09d35b5a7ecatree | snapshot
parent63a92fe6f7e40069086be21bf9fbcfbe8d001345commit | diff
cxgb4: Fix T5 adapter accessing T4 adapter registers

Fixes few register access for both T4 and T5.
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS & PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS
is T4 only register don't let T5 access them. For T5 MA_PARITY_ERROR_STATUS2
is additionally read. MPS_TRC_RSS_CONTROL is T4 only register, for T5 use
MPS_T5_TRC_RSS_CONTROL.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c diff | blob | history
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c diff | blob | history
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h diff | blob | history
Domain: System / Kernel;