intel/compiler: fix generation of vec8/vec16 alu instruction
authorMarcin Ślusarz <marcin.slusarz@intel.com>
Thu, 12 Jan 2023 15:06:42 +0000 (16:06 +0100)
committerMarge Bot <emma+marge@anholt.net>
Tue, 24 Jan 2023 13:15:58 +0000 (13:15 +0000)
commit9bb18a4f9ee300b566e642e6960479b63cf8f011
tree94db14b5e301e2a3729f9e47e142ec9a3bfd431b
parent19b0bafe35308d67c57ec6d0b2cfb02d219cd5bd
intel/compiler: fix generation of vec8/vec16 alu instruction

I stumbled on this when I inserted some suboptimal lowering code after all
optimizations. Adding certain subset of optimizations after my lowering code
actually avoided this bug, so I think it's not possible to hit this on upstream.

Let's fix this for the next person generating suboptimal code...

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20857>
src/intel/compiler/brw_fs_nir.cpp