arm: am33xx: Avoid writing into reserved DPLL divider
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 28 Dec 2017 15:10:01 +0000 (20:40 +0530)
committerTom Rini <trini@konsulko.com>
Fri, 19 Jan 2018 20:49:24 +0000 (15:49 -0500)
commit9b88a4bda2955b23262736d70e5c3d3c36685db0
tree56be0a56d3509e7c5a7a1f8a619aaff07ec540a1
parent3a0e70f181ecf21db2486c289055d4269887cab8
arm: am33xx: Avoid writing into reserved DPLL divider

DPLL DRR doesn't have an M4 divider. But the clock driver is trying
to configure M4 divider as 4(writing into a reserved register).
Fixing it by making M4 divider as -1.

Reported-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/mach-omap2/am33xx/clock_am33xx.c