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(parent: 8d68821) | patch
arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core
authorFabrizio Castro <fabrizio.castro@bp.renesas.com>
Fri, 14 Dec 2018 09:10:13 +0000 (09:10 +0000)
committerSimon Horman <horms+renesas@verge.net.au>
Tue, 22 Jan 2019 14:42:27 +0000 (15:42 +0100)
commit9b55a05ebfbe41bfb4c2aa98a81a46f2031e599f
tree79bcbb71491978f7671aa63fb335a3ffdc48f756tree | snapshot
parent8d68821ced28391551b5e2014de4b1bf461b667ecommit | diff
arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core

Add a device node for the second Cortex-A53 CPU core on the Renesas
RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
for the ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a774c0.dtsi diff | blob | history
Domain: System / Kernel;