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(parent: 14b14a5) | patch
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 13 Jul 2023 11:38:56 +0000 (19:38 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 19 Jul 2023 17:08:00 +0000 (18:08 +0100)
commit9b3938c0b81e79e1c0e1a3e95be3e12efd8c771b
treebe1dd5142a92968b5756b99893f4f69ea145dc0dtree | snapshot
parent14b14a57e642e0dab9be4e9d0866fb2c4332f7c5commit | diff
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;