projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9fdf21f) | patch
[RISCV] Check the sign bits of the input of RISCVISD::ABSW in computeNumSignBitsForTa...
authorCraig Topper <craig.topper@sifive.com>
Wed, 21 Dec 2022 20:50:10 +0000 (12:50 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 21 Dec 2022 20:56:35 +0000 (12:56 -0800)
commit9b227cb1f536829ce109f7334beceb71f804d58b
tree7d606037a3e98640849fa0be4224cf368196f198tree | snapshot
parent9fdf21f3d07d5efafec4334b1b4d200bc7811c05commit | diff
[RISCV] Check the sign bits of the input of RISCVISD::ABSW in computeNumSignBitsForTargetNode.

We created a SIGN_EXTEND_INREG when we created the ABSW so the
input should have 33 sign bits, but check it to be safe.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
Domain: System / Toolchain;