drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming
authorGeorge Shen <george.shen@amd.com>
Thu, 11 Aug 2022 02:06:17 +0000 (22:06 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 29 Aug 2022 21:45:10 +0000 (17:45 -0400)
commit9af611f29034dd6c9329de06dc98232a5b89b939
treea1a13eff201e29970481f451323a4e57c55b36b4
parenta3c9b4c7a75a66b65b62900e2e9d140e0470cd85
drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming

[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.

Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-to-1 with
HPO stream encoder instance. This is not always
guaranteed and can result in blackscreen.

[How]
Program the correct dpstreamclk instance with
the correct dtbclk_p source.

Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c