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(parent: 7a2c8be) | patch
[RISCV] Define vector compare intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Tue, 15 Dec 2020 23:06:07 +0000 (07:06 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Tue, 22 Dec 2020 06:08:18 +0000 (14:08 +0800)
commit9a8ef927df38a933909a512bf0089a28387ad876
treeef21ace8c1bacc4795880d44309904b8b285d42ftree | snapshot
parent7a2c8be641ded68b3424b46dbf47f2879a9eaa2ecommit | diff
[RISCV] Define vector compare intrinsics.

Define vector compare intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>
Differential Revision: https://reviews.llvm.org/D93368
30 files changed:
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll [new file with mode: 0644] blob
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