RISC-V: Add perf platform driver based on SBI PMU extension
authorAtish Patra <atish.patra@wdc.com>
Wed, 17 Mar 2021 23:54:14 +0000 (16:54 -0700)
committerminda.chen <minda.chen@starfivetech.com>
Tue, 3 Jan 2023 06:26:17 +0000 (14:26 +0800)
commit9a7e4fe5717564dfbd317990b50eddb42bb36ae8
tree8529a4f0c4d4b704605864828503fce52e127ff8
parent81d8564c1fe8b70cf362f4d919cc83cdef8c6101
RISC-V: Add perf platform driver based on SBI PMU extension

RISC-V SBI specification added a PMU extension that allows to configure
start/stop any pmu counter. The RISC-V perf can use most of the generic
perf features except interrupt overflow and event filtering based on
privilege mode which will be added in future.

It also allows to monitor a handful of firmware counters that can provide
insights into firmware activity during a performance analysis.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
drivers/perf/Kconfig
drivers/perf/Makefile
drivers/perf/riscv_pmu.c
drivers/perf/riscv_pmu_sbi.c [new file with mode: 0644]
include/linux/cpuhotplug.h
include/linux/perf/riscv_pmu.h