projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b2bd281) | patch
[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
authorJustin Holewinski <jholewinski@nvidia.com>
Mon, 2 May 2016 18:12:02 +0000 (18:12 +0000)
committerJustin Holewinski <jholewinski@nvidia.com>
Mon, 2 May 2016 18:12:02 +0000 (18:12 +0000)
commit9a6ea2c2566d32a23db43ed9108d6e4c048faf55
tree74e8618c55f907148d0ecfa74eac53cbfab18d6ftree | snapshot
parentb2bd28128dafe1cbc9e31f230dcd2ded9fd02168commit | diff
[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection

Summary:
We don't have sign-/zero-extending ldg/ldu instructions defined,
so we need to emulate them with explicit CVTs. We were originally
handling the i8 case, but not any other cases.

Fixes PR26185

Reviewers: jingyue, jlebar

Subscribers: jholewinski

Differential Revision: http://reviews.llvm.org/D19615

llvm-svn: 268272
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h diff | blob | history
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td diff | blob | history
llvm/test/CodeGen/NVPTX/bug26185-2.ll [new file with mode: 0644] blob
Domain: System / Toolchain;