intel/nir: Limit unaligned loads to vec4
authorFaith Ekstrand <faith.ekstrand@collabora.com>
Sat, 25 Feb 2023 00:04:49 +0000 (18:04 -0600)
committerMarge Bot <emma+marge@anholt.net>
Fri, 3 Mar 2023 02:00:39 +0000 (02:00 +0000)
commit9a4641cf6b669598d270117e5c64653db6e7db65
treed46f475e0598f73c66c6f6b0e4d590de6592e383
parentc11ac5e4462c5aceb35958858f6cef93d142c7de
intel/nir: Limit unaligned loads to vec4

This probably doesn't affect Vulkan or GL because they can't have
anything bigger than a vec4 anyway unless it's a u64vec4 and those have
to be at least 8B aligned.  This may affect CL apps if they use
__attribute__((packed)) on something with big vectors, depending on how
LLVM decides to translate that.

Fixes: f8aa83f0c86e ("intel/nir: Use nir_lower_mem_access_bit_sizes()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21524>
src/intel/compiler/brw_nir.c