drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
authorJesse Barnes <jbarnes@virtuousgeek.org>
Fri, 26 Oct 2012 16:42:42 +0000 (09:42 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sun, 11 Nov 2012 22:51:36 +0000 (23:51 +0100)
commit9a28977181724ebbd9bdc45291cf29da55a729ee
treed83f779436fcaab0b445c64ee50252269ba6b211
parent12f3382bc0262e981a2e58aca900cbbdbbe66825
drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3

So store into the scratch space of the HWS to make sure the invalidate
occurs.

v2: use GTT address space for store, clean up #defines (Chris)
v3: use correct #define in blt ring flush (Chris)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h