projects / contrib / beignet.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 552eae5) | patch
GBE: Fix one bug in instruction scheduling.
authorZhigang Gong <zhigang.gong@gmail.com>
Thu, 8 Aug 2013 07:15:44 +0000 (15:15 +0800)
committerZhigang Gong <zhigang.gong@linux.intel.com>
Fri, 9 Aug 2013 15:29:30 +0000 (23:29 +0800)
commit9a2760d421b70def9f3974bc2d2c4df2dbf5df20
treeb3a56f65e97f4a86152024625453aa1bb29290d6tree | snapshot
parent552eae5f4c5d063038244ac3d11e2a0fc427e849commit | diff
GBE: Fix one bug in instruction scheduling.

As now we may use 8 byte registers (long and double), then one
register may take two(SIMD8) or four(SIMD16) physical registers.
Thus if we met a register with long or double type, we need to
handle the immediately next index at the same time.

Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
backend/src/backend/gen_insn_scheduling.cpp diff | blob | history
Domain: SCM / Uncategorized;