RISC-V: Avoid using per cpu array for ordered booting
authorAtish Patra <atishp@rivosinc.com>
Thu, 20 Jan 2022 09:09:13 +0000 (01:09 -0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 20 Jan 2022 17:26:59 +0000 (09:26 -0800)
commit9a2451f1866344d38b4a1dc20396e3a03954fcd7
tree554497f0f45fad78ebdbed0e32e3470eea8adbbc
parent3938d5a2f9369d1ebd56320629fed395ce327e9c
RISC-V: Avoid using per cpu array for ordered booting

Currently both order booting and spinwait approach uses a per cpu
array to update stack & task pointer. This approach will not work for the
following cases.
1. If NR_CPUs are configured to be less than highest hart id.
2. A platform has sparse hartid.

This issue can be fixed for ordered booting as the booting cpu brings up
one cpu at a time using SBI HSM extension which has opaque parameter
that is unused until now.

Introduce a common secondary boot data structure that can store the stack
and task pointer. Secondary harts will use this data while booting up
to setup the sp & tp.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/cpu_ops_sbi.h [new file with mode: 0644]
arch/riscv/kernel/asm-offsets.c
arch/riscv/kernel/cpu_ops_sbi.c
arch/riscv/kernel/head.S