AArch64: Gate various crypto intrinsics availability based on features

AArch64: Gate various crypto intrinsics availability based on features

The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES
is implemented according to the Arm ARM [1].  Similarly FEAT_SHA1 and
FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants.
This patch fixes arm_neon.h to correctly reflect the feature availability based
on '+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'.

[1] Section D17.2.61, C7.2.215

2022-01-11  Tejas Belagod  <tejas.belagod@arm.com>

gcc/ChangeLog:

	* config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8,
	vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes".
	(vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2".

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/pmull64.c: New.
	* gcc.target/aarch64/aes-fuse-1.c: Replace '+crypto' with corresponding
	feature flag based on the intrinsic.
	* gcc.target/aarch64/aes-fuse-2.c: Likewise.
	* gcc.target/aarch64/aes_1.c: Likewise.
	* gcc.target/aarch64/aes_2.c: Likewise.
	* gcc.target/aarch64/aes_xor_combine.c: Likewise.
	* gcc.target/aarch64/sha1_1.c: Likewise.
	* gcc.target/aarch64/sha256_1.c: Likewise.
	* gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.