review.tizen.org Git - contrib/beignet.git/commit

author	Zhigang Gong <zhigang.gong@intel.com>
	Wed, 21 May 2014 08:27:55 +0000 (16:27 +0800)
committer	Zhigang Gong <zhigang.gong@intel.com>
	Tue, 27 May 2014 02:20:31 +0000 (10:20 +0800)
commit	99d079552ecfca2611b94a1fe51da181b2dd7d9d
tree	b06bd86e3893748e086da8c580d1fda2957541aa	tree \| snapshot
parent	c90c4759119a78f89f27b8a384631adcc5040e78	commit \| diff

GBE: fix post scheduling related bug for spill/unspill.

spill/unspill instruction touch some registers directly which
are not in dst/src. This breaks the post scheduling. Simply
work around it by add all the reserved registers to the dst
array.

The scratch memory is not correctly indexed and the barrier is
not handled properly.

After this patch, the post scheduling will be enabled by default.

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>

backend/src/backend/gen_insn_scheduling.cpp		diff \| blob \| history
backend/src/backend/gen_insn_selection.cpp		diff \| blob \| history
backend/src/backend/gen_reg_allocation.cpp		diff \| blob \| history