[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.
authorZakk Chen <zakk.chen@sifive.com>
Thu, 11 Mar 2021 16:01:04 +0000 (08:01 -0800)
committerZakk Chen <zakk.chen@sifive.com>
Wed, 17 Mar 2021 17:47:49 +0000 (10:47 -0700)
commit9998b00c2ecd480c54d3fe806c4011439e41b065
treee53030553f49a39c5b5088763e770c50149c4a45
parente2935dcfc4c4ecd93ca39054f0df500b2d28a75f
[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

Fix the unexpected of using op1's element type as shift amount type.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98501
18 files changed:
llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll