NET: stmmac: align DMA stuff to largest cache line length
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Thu, 26 Jul 2018 12:05:37 +0000 (15:05 +0300)
committerDavid S. Miller <davem@davemloft.net>
Sun, 29 Jul 2018 19:33:30 +0000 (12:33 -0700)
commit9939a46d90c6c76f4533d534dbadfa7b39dc6acc
treee8f9af52182bc85cf5af89556c393280320bb151
parent383d470936c05554219094a4d364d964cb324827
NET: stmmac: align DMA stuff to largest cache line length

As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
relies on L1 line length (L1_CACHE_BYTES).
This isn't correct in case of system with several cache levels
which might have L1 cache line length smaller than L2 line. This
can lead to sharing one cache line between DMA buffer and other
data, so we can lose this data while invalidate DMA buffer before
DMA transaction.

Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
aligning.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c