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(parent: 445c8cf) | patch
phy: cadence: Sierra: Add PHY PCS common register configurations
authorSwapnil Jakhade <sjakhade@cadence.com>
Fri, 28 Jan 2022 08:11:44 +0000 (13:41 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 16:00:03 +0000 (11:00 -0500)
commit990ce535ebc3f912769cbc8a651b7eb53545c60d
tree0fe5d9dd4d0bb149f3f6fd30347d4a930b71aaeatree | snapshot
parent445c8cf89b7472a6a78854f87de114bc067c1878commit | diff
phy: cadence: Sierra: Add PHY PCS common register configurations

Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
Domain: System / Kernel;