[RISCV] Add isel patterns for SBCLRI/SBSETI/SBINVI(W) instruction
authorCraig Topper <craig.topper@sifive.com>
Tue, 8 Dec 2020 19:29:05 +0000 (11:29 -0800)
committerCraig Topper <craig.topper@sifive.com>
Tue, 8 Dec 2020 20:22:40 +0000 (12:22 -0800)
commit98bca0a60574c4276cfc85833fe29d8f4beff7f6
tree1a960df682a566db2cd7e26cf4be48280d744f20
parentabd80ac9b83c09b98b6b0bb3f2d4630d37e070ef
[RISCV] Add isel patterns for SBCLRI/SBSETI/SBINVI(W) instruction

We can use these instructions for single bit immediates that are too large for ANDI/ORI/CLRI.

The _10 test cases are to make sure that we still use ANDI/ORI/CLRI for small immediates.

Differential Revision: https://reviews.llvm.org/D92262
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbs.ll
llvm/test/CodeGen/RISCV/rv32Zbt.ll
llvm/test/CodeGen/RISCV/rv64Zbb.ll
llvm/test/CodeGen/RISCV/rv64Zbs.ll