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drm/i915: Program DPLL P1 dividers consistently
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 15 Jul 2021 09:35:25 +0000 (12:35 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 25 Aug 2021 14:11:10 +0000 (17:11 +0300)
commit98b27e79898b5f5a15734525c7a31f67f7a9766a
tree7445ab7f3ff3add0c753f2118421cde9d59ba678tree | snapshot
parent510e890e8222443bbfc74083cb8e0797665fcaaacommit | diff
drm/i915: Program DPLL P1 dividers consistently

On g4x and pch the DPLL has two P1 dividers (for refresh rate
switching). Program the FPx1 P1 divider consistently to the reduced
clock P1 divider if available, otherwise just program it to the
same value as the FPx0 P1 divider.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_dpll.c diff | blob | history
Domain: System / Kernel;