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(parent: d7803c3) | patch
Update LSR's logic that identifies a post-increment SCEV value.
authorSumanth Gundapaneni <sgundapa@quicinc.com>
Mon, 2 Mar 2020 22:32:19 +0000 (16:32 -0600)
committerSumanth Gundapaneni <sgundapa@quicinc.com>
Mon, 2 Mar 2020 22:34:18 +0000 (16:34 -0600)
commit9897daa6bfcce044473f63e12492ec7748e8eb62
treee9434cf0a51f44c7ca4e12b9ab49def0b6fde366tree | snapshot
parentd7803c38327dbc8d047c542b5acda0bb946a4008commit | diff
Update LSR's logic that identifies a post-increment SCEV value.

One of the checks has been removed as it seem invalid.
The LoopStep size is always almost a 32-bit.

Differential Revision: https://reviews.llvm.org/D75079
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff | blob | history
llvm/test/CodeGen/Hexagon/addrmode-align.ll diff | blob | history
llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll [new file with mode: 0644] blob
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll diff | blob | history
Domain: System / Toolchain;