[ARM] WLS/LE Code Generation
authorSam Parker <sam.parker@arm.com>
Mon, 1 Jul 2019 08:21:28 +0000 (08:21 +0000)
committerSam Parker <sam.parker@arm.com>
Mon, 1 Jul 2019 08:21:28 +0000 (08:21 +0000)
commit98722691b0b5e375fdd02c9a464476752a3c598e
tree749462ab6f4a19ba537c95094b76cf4cb9ebe44e
parent0384a780549a0b87cefc3e7d787787a5e5bb9527
[ARM] WLS/LE Code Generation

Backend changes to enable WLS/LE low-overhead loops for armv8.1-m:
1) Use TTI to communicate to the HardwareLoop pass that we should try
   to generate intrinsics that guard the loop entry, as well as setting
   the loop trip count.
2) Lower the BRCOND that uses said intrinsic to an Arm specific node:
   ARMWLS.
3) ISelDAGToDAG the node to a new pseudo instruction:
   t2WhileLoopStart.
4) Add support in ArmLowOverheadLoops to handle the new pseudo
   instruction.

Differential Revision: https://reviews.llvm.org/D63816

llvm-svn: 364733
22 files changed:
llvm/lib/CodeGen/HardwareLoops.cpp
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/cond-mov.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll [new file with mode: 0644]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/massive.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/multiblock-massive.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/revert-after-call.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/revert-after-spill.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir [new file with mode: 0644]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/size-limit.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir [moved from llvm/test/Transforms/HardwareLoops/ARM/switch.mir with 100% similarity]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir [new file with mode: 0644]
llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll
llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll
llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll
llvm/test/Transforms/HardwareLoops/ARM/structure.ll