[RISCV] Implement vloxseg/vluxseg intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Mon, 18 Jan 2021 02:02:40 +0000 (10:02 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sat, 23 Jan 2021 00:54:56 +0000 (08:54 +0800)
commit97e33feb08aa9c042408862e555423f037753e12
tree88d701974e8f13a16be63134d277f8b7f232307a
parentef51eed37b7ed67b3c0e5f70fa61d681ba21787d
[RISCV] Implement vloxseg/vluxseg intrinsics.

Define vloxseg/vluxseg intrinsics and pseudo instructions.
Lower vloxseg/vluxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94903
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td