projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: bea661d) | patch
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0
authorShihPo Hung <shihpo.hung@sifive.com>
Tue, 19 Jan 2021 09:07:34 +0000 (01:07 -0800)
committerShihPo Hung <shihpo.hung@sifive.com>
Fri, 22 Jan 2021 02:38:49 +0000 (18:38 -0800)
commit976cf53cc7a5dd03932a6e44b8a9350a05cdaa68
treec26f376d000fb50bce3549c41ddc4e0b8084dc22tree | snapshot
parentbea661d9a52f9abb4fef7cf195092e912c165d34commit | diff
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0

Add unordered indexed load: vluxei

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95028
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll [new file with mode: 0644] blob
Domain: System / Toolchain;