[AArch64][ARM] Don't base interleaved op legality on type alloc size.
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Wed, 9 Dec 2015 01:19:50 +0000 (01:19 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Wed, 9 Dec 2015 01:19:50 +0000 (01:19 +0000)
commit97564c3a1b015a5212cab9dfe048425fcb00ff97
tree0735ff9dc9cbc6637af62b4ce9304275d89fd324
parentb8dced5dfa3b5abba27898dfd0a8341995756584
[AArch64][ARM] Don't base interleaved op legality on type alloc size.

Otherwise, we think that most types that look like they'd fit in a
legal vector type are legal (so, basically, *any* vector type with a
size between 33 and 128 bits, I think, since we use pow2 alignment;
e.g., v2i25, v3f32, ...).

DataLayout::getTypeAllocSize rounds up based on alignment.
When checking for target intrinsic legality, that's not what we want:
if rounding makes a difference, the type isn't legal, and the
target intrinsics shouldn't be used, as they are always assumed legal.

One could make the argument that alloc size is ultimately the most
relevant here, since we're dealing with LD/ST intrinsics. That's only
true if we did legalize them though; that's a problem for another day.

Use DataLayout::getTypeSizeInBits instead of getTypeAllocSizeInBits.
Type::getSizeInBits can't be used because that'd gratuitously break
pointer vector support.

Some of these uses are currently fine, because we only hit them when
the type is already known legal (e.g., r114454). Update them for
consistency. It's faster to avoid the rounding anyway!

llvm-svn: 255089
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll
llvm/test/CodeGen/ARM/arm-interleaved-accesses.ll