[include/opcode/]
authorRichard Sandiford <rdsandiford@googlemail.com>
Mon, 30 Sep 2002 11:58:10 +0000 (11:58 +0000)
committerRichard Sandiford <rdsandiford@googlemail.com>
Mon, 30 Sep 2002 11:58:10 +0000 (11:58 +0000)
commit9752cf1b67871d71ba4ccaf358e7550979bb4a3c
tree9cea29ddfab8c889581cdbab6d8958497d7aad6e
parent00707a0e8939f67d5287bcc91c951006337e7e15
[include/opcode/]
* mips.h: Update comment for new opcodes.
(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
Don't match CPU_R4111 with INSN_4100.

[opcodes/]
* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
and bfd_mach_mips5500.
* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
(N411, N412, N5, N54, N55): New convenience defines.
(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
Change dmadd16 and madd16 from V1 to N411.
include/opcode/ChangeLog
include/opcode/mips.h
opcodes/ChangeLog
opcodes/mips-dis.c
opcodes/mips-opc.c