[RISCV] Adjust RV64I data layout by using n32:64 in layout string
authorCraig Topper <craig.topper@sifive.com>
Fri, 28 Oct 2022 15:13:35 +0000 (08:13 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 28 Oct 2022 15:27:03 +0000 (08:27 -0700)
commit974e2e690b4024c2677dde26cc76ec31e0047c1d
treef0912eef57e9cf703626c85712cd3eeca618a073
parent4b0c285ef24039146fa6eee39b614820664987a0
[RISCV] Adjust RV64I data layout by using n32:64 in layout string

Although i32 type is illegal in the backend, RV64I has pretty good support for i32 types by using W instructions.

By adding n32 to the DataLayout string, middle end optimizations will consider i32 to be a native type. One known effect of this is enabling LoopStrengthReduce on loops with i32 induction variables. This can be beneficial because C/C++ code often has loops with i32 induction variables due to the use of `int` or `unsigned int`.

If this patch exposes performance issues, those are better addressed by tuning LSR or other passes.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D116735
clang/lib/Basic/Targets/RISCV.h
llvm/docs/ReleaseNotes.rst
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/aext-to-sext.ll
llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp