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[RISCV] Model vlseg/vsseg in interleaved memory ops
authorLuke Lau <luke@igalia.com>
Tue, 21 Mar 2023 13:02:16 +0000 (13:02 +0000)
committerLuke Lau <luke@igalia.com>
Tue, 4 Apr 2023 14:05:14 +0000 (15:05 +0100)
commit971a4501f7f2017816e3365f0008418fd978a9e7
treef9ab3c93292216a38fe526afec1ae25af6d175a8tree | snapshot
parentb4089cfa2fc3449a2e124804d34ba8fb591e55c5commit | diff
[RISCV] Model vlseg/vsseg in interleaved memory ops

If the legalized type is a legal interleaved access type (i.e. there's a
supported vlseg/vsseg instruction for it), the interleaved access pass
will pick any interleaved memory op (wide load + shuffles) and lower it
into a vlseg/vsseg intrinsic.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D146522
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp diff | blob | history
llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll diff | blob | history
llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll diff | blob | history
Domain: System / Toolchain;