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(parent: 9db1bfa) | patch
mx53: ddr3: Update DD3 initialization
authorFabio Estevam <festevam@gmail.com>
Fri, 19 Aug 2011 03:28:10 +0000 (03:28 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 4 Sep 2011 09:36:11 +0000 (11:36 +0200)
commit9691c5b96d889b1d4c8908c449b47d80699dc915
tree9e1476e7354da652274b1f7b95fbed7c59ce766ctree | snapshot
parent9db1bfa110ac411ab3468e817f7f74b2439eb8c8commit | diff
mx53: ddr3: Update DD3 initialization

Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])

Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
board/freescale/mx53ard/imximage_dd3.cfg diff | blob | history
board/freescale/mx53loco/imximage.cfg diff | blob | history
board/freescale/mx53smd/imximage.cfg diff | blob | history
Domain: System / Kernel;