Revert "[ARM] Add CPSR as an implicit use of t2IT"
authorSam Parker <sam.parker@arm.com>
Thu, 27 Feb 2020 15:36:53 +0000 (15:36 +0000)
committerSam Parker <sam.parker@arm.com>
Thu, 27 Feb 2020 15:43:44 +0000 (15:43 +0000)
commit965ba4291a6d978c7d4d98831d6ae62e9761f37d
tree3c464c0f2952d45d2758dbe7c4d14f4afd917329
parentf943443e65115c83648f1185adedb3d333f8619f
Revert "[ARM] Add CPSR as an implicit use of t2IT"

This reverts commit e58229fded0407f3e4f77cd87bedcd4d35bb7c89.

Differential Revision: https://reviews.llvm.org/D75186
46 files changed:
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
llvm/test/CodeGen/ARM/tail-dup-bundle.mir
llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir
llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir
llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir