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[Cortex-M0] Atomic lowering
authorWeiming Zhao <weimingz@codeaurora.org>
Thu, 3 Nov 2016 21:49:08 +0000 (21:49 +0000)
committerWeiming Zhao <weimingz@codeaurora.org>
Thu, 3 Nov 2016 21:49:08 +0000 (21:49 +0000)
commit962eaaea9c9ea5cff2254b1251474029e4fe6a3d
tree5038d15eb2b2989a9964644888634950bc341d64tree | snapshot
parent5bc0323c11f88580de66acbd588ddef8d986329bcommit | diff
[Cortex-M0] Atomic lowering

Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls.

Reviewers: rengolin, efriedma, t.p.northover, jmolloy

Subscribers: efriedma, aemerson, llvm-commits

Differential Revision: https://reviews.llvm.org/D26120

llvm-svn: 285969
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/lib/Target/ARM/ARMSubtarget.cpp diff | blob | history
llvm/test/CodeGen/ARM/atomic-op.ll diff | blob | history
Domain: System / Toolchain;